3.0 GB S, 272 MW, 8/1 MULTIPLEXER AND 4.1 GB/S, 388 MW, 1/8 DEMULTIPLEXER/

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fi ber optic transmission systems. These chips incorporate new architectu res having a smaller hardware and enabling the use of a lower supply v oltage. The multiplexer and the demultiplexer are fabricated using 0.8 mu m silicon-bipolar process with a double polysilicon self-aligned s tructure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, wh ile the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The mu ltiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE = -4.0 V and VTT = -2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Lev el -16 of the synchronous transfer mode (STM-16).