In this paper we present a timing-influenced floorplanner for general
cell IC design. The floorplanner works in two phases. In the first pha
se we use the genetic algorithm and restrict the modules to be rigid a
nd the floorplan to have slicing structure. This restriction results i
n a simple and elegant encoding, as well as large savings in run time.
In this phase the search is directed toward floorplans that better sa
tisfy timing constraints on the critical paths and delay bounds on all
the nets. The objective function also incorporates area and wire-leng
th. The second phase allows modification to the aspect ratios of indiv
idual modules to reduce further the area of the overall bounding box.
This phase is constraint graph based. The approach combines the robust
ness of genetic algorithm with run time efficiency and elegance of con
straint graph based method. Experimental results are presented. (C) 19
97 Elsevier Science Ltd.