VLSI IMPLEMENTATION OF INVERSE DISCRETE COSINE TRANSFORMER AND MOTIONCOMPENSATOR FOR MPEG2 HDTV VIDEO DECODING

An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High L evel) images is described with the main theme focused on an inverse di screte cosine transformer and a motion compensator. By means of variou s novel architectures, the inverse discrete cosine transformer achieve s a high throughput, and the motion compensator performs different typ es of picture prediction modes employed by the MPEG2 algorithm. The de coder core, implemented in the total chip area of 22.0 mm(2) by a 0.6- mu m triple-metal CMOS technology, processes a macroblock within 3.84 mu s, and therefore is capable of decoding HDTV (1920 x 1152 pels) ima ges in real time.