VLSI ARCHITECTURE FOR A FLEXIBLE BLOCK MATCHING PROCESSOR

A flexible and powerful VLSI architecture for the implementation of a wide spectrum of full search and reduced complexity search block match ing algorithms is presented. Optimized efficiency for variable algorit hm parameters is obtained by using a quadratic systolic array architec ture with global accumulation, combined with a flexible meander-like d ata flow. Flexibility is further increased by cascadability and/or the possibility of parallel operation. Hardware overhead for particular a lgorithmic requirements, such as variable pixel resolution, sub-sampli ng with offset, and subpixel accuracy, is discussed in detail. A full- custom implementation for the architecture is described.