A SINGLE-CHIP VIDEO SIGNAL-PROCESSING ARCHITECTURE FOR IMAGE-PROCESSING, CODING, AND COMPUTER VISION

Citation
J. Goodenough et al., A SINGLE-CHIP VIDEO SIGNAL-PROCESSING ARCHITECTURE FOR IMAGE-PROCESSING, CODING, AND COMPUTER VISION, IEEE transactions on circuits and systems for video technology, 5(5), 1995, pp. 436-445
Citations number
15
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
10518215
Volume
5
Issue
5
Year of publication
1995
Pages
436 - 445
Database
ISI
SICI code
1051-8215(1995)5:5<436:ASVSAF>2.0.ZU;2-E
Abstract
A new VLSI architecture for an internally multiprocessing, single chip , SIMD-based Video Signal Processor (VSP) is presented. The limitation s of extended DSP architectures and conventional Array Processors are discussed in the context of image processing, coding and computer visi on, How this gives rise to the architecture is described, Architectura l flexibility is provided by the integration of a novel array-based pr ocessing core, together with a RISC Processor, Intelligent Memory Inte rface Processor, and internal cache RAM. The array core architecture i s a second generation, enhanced array whose key features are: 2 b data path, dual processor mesh-connected array planes and combined SIMD/Sys tolic functionality, The core is optimized for 2-D windowed operations , particularly 2-D multiply-accumulation and transforms, The device is expected to operate at 80 MHz on low voltage silicon and deliver real -time performance across a range of target applications.