A COMPACT REAL-TIME VISION SYSTEM USING INTEGRATED MEMORY ARRAY PROCESSOR ARCHITECTURE
Citation
S. Okazaki et al., A COMPACT REAL-TIME VISION SYSTEM USING INTEGRATED MEMORY ARRAY PROCESSOR ARCHITECTURE, IEEE transactions on circuits and systems for video technology, 5(5), 1995, pp. 446-452
Categorie Soggetti
Engineering, Eletrical & Electronic
SICI code
1051-8215(1995)5:5<446:ACRVSU>2.0.ZU;2-S
Abstract
This paper describes Real-Time Vision System (RVS-2) which shows quite
high performance for low-level image processing while it is implement
ed in one-board type compact size with small power consumption, RVS-2
consists of an IMAP board, a video board and a host workstation, and t
he IMAP board consists of eight highly-integrated IMAP LSI's and a ded
icated control LSI(RVSC), The IMAP chip integrates 2 Mb image memory a
nd 64 processing elements that operate in SIMD fashion. The RVSC chip
has functions to carry out global data operations efficiently without
interactions with the host workstation, as well as the functions for p
roviding an instruction stream to IMAP chips, The peak performance of
RVS-2 is 30 GIPS and most of basic image processing are carried out wi
thin about 0.1-0.7 ms, which is about 50-300 times faster than the vid
eo frame rate.