Qh. Wu et al., LILA - LAYOUT GENERATION FOR ITERATIVE LOGIC-ARRAYS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(11), 1995, pp. 1359-1369
A CAD tool, LILA, that generates layouts of both one-dimensional and t
wo-dimensional iterative logic arrays, described in VHDL or schematic
structures, is presented, Such a tool is very important because in cur
rent industry, the generation of high density iterative logic arrays (
such as data path in microprocessors) is still mainly performed manual
ly, and is a major bottleneck of the design, In LILA, interconnections
between modules (i.e., cells) of the array do not need to be between
adjacent modules and functions of modules of the array do not need to
be identical, Regularity in module functions and interconnections betw
een modules are automatically extracted by the tool, Based on intercon
nection wire length between modules, layouts of modules and interconne
ctions are optimized in a single step, The signals in each array modul
e are generated in such a way that signals in adjacent modules are per
fectly aligned and connected by module abutments, As no global routing
or channel routing between modules are necessary, the total layout ar
ea and propagation delay between modules are minimal. The proposed sys
tem is especially useful for data path modules, bit-level systolic arr
ays, storage devices, and many other regular structures, and has been
actually implemented in a design environment, Extensive experiments ha
ve shown that the system has a very good performance and produces layo
uts of very high density, The tool takes about 1.6 CPU seconds to gene
rate an eight-by-eight array divider on a SUN SPARC station II.