O. Kaser, ON SQUASHING HIERARCHICAL DESIGNS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(11), 1995, pp. 1398-1402
The problem of partially expanding a hierarchical VLSI design is exami
ned, with the goal of reducing the number of levels of hierarchy while
incurring minimal design-size expansion, While the general problem ap
pears NP-hard, an important special case is considered, where the numb
er of levels of hierarchy is reduced by one, For this special case, an
exact algorithm is developed, based on network-flow techniques. Using
this algorithm, a heuristic for the general problem is then developed
and experimentally evaluated on a collection of VLSI designs.