TEST-GENERATION FOR CYCLIC COMBINATIONAL-CIRCUITS

Circuits that have an underlying acyclic topology are guaranteed to be combinational since feedback is necessary for sequential behavior, Ho wever, the reverse is not true, i.e., feedback is not a sufficient con dition since there do exist combinational logic circuits that are cycl ic. In fact, such combinational circuits occur often in bus structures in data paths. This class of circuits has largely been ignored by con ventional combinational single-stuck-at fault test pattern generators which assume that the circuit topology is acyclic, There has not been a formal study of the test generation problem for these circuits, Also , no algorithms and tools exist for this purpose, In practice, test ge neration for these circuits is handled in an awkward manner, typically with poor fault coverage. This work provides, for the first time, a f ormal analysis of the test generation problem for these circuits, This analysis leads to a clear Insight into generation of tests, as well a s a classification of untestable faults for such circuits, We demonstr ate that cyclic combinational circuits may have untestable faults that do not correspond to redundancies, This insight is then translated to a testing algorithm which has been implemented in the program RAM. RA M has been successful in providing complete or near complete coverage on a range of typical examples, which is significantly higher than tha t provided by conventional techniques.