A SYSTEMATIC METHODOLOGY FOR MAPPING DSP ALGORITHMS ONTO MULTILEVEL ARRAY ARCHITECTURES

In this paper, a systematic graph-based methodology for designing syst olic arrays, which can perform concurrently, is introduced. Partitioni ng a DSP iterative algorithm into a number of sub-algorithms, we descr ibe each of them, along with their interdependences, with a set of Uni form Recurrent Equations. Alternative architectures can be designed by mapping the dependence graph of the algorithm onto hardware. The main feature of the proposed architectures is the significant reduction of the computation time of the algorithm.