ONE-BIT ADDER DESIGN BASED ON REED-MULLER EXPANSIONS

It has been claimed for some time that the Reed-Muller technique can y ield a simpler arithmetic circuit if it is employed in the design proc edure. In fact, no practical application in this field can be found in the open literature. This paper attempts to demonstrate a practical o ne-bit adder design that is based on the Reed-Muller expansion. Althou gh the one-bit adder is simple, no method can always guarantee to obta in both a time and area optimal circuit. In this paper, a procedure to design both a time and area optimal one-bit adder in static CMOS circ uits is presented. Some issues are also addressed for practical logic circuit design.