USING TIME ZONES FOR DATA-PATH ALLOCATION IN HIGH-LEVEL SYNTHESIS OF DIGITAL-SYSTEMS

The paper describes the data path allocation in high-level synthesis o f digital systems using a new approach named the time-zone approach. U sing the time-zone approach, where time steps are partitioned into zon es, the register allocation and the module allocation for a given sche duled data flow graph (DFG) are performed in the same phase. The numbe r of registers required to store the values in the DFG is minimized, a nd at the same time the interconnections between the registers and the modules (as well as the number of multiplexers required) are optimize d. The experimental results obtained from testing several published be nchmarks show that the allocation results are improved in terms of red uction of interconnections and the number of multiplexers and register s.