ONE-DIMENSIONAL ANALYTICAL MODELING OF THE VDMOS TRANSISTOR TAKING INTO ACCOUNT THE THERMOELECTRICAL INTERACTIONS

An analytical one-dimensional thermoelectrical model for the power MOS FET transistor (VDMOS transistor) has been developed and implemented i n the Saber circuit simulator, The device temperature becomes an inter active variable during the simulation, The model results in the combin ation of the electrical model of the device with a thermal network whi ch models the different material layers crossed by the heat flow from the silicon chip to the heatsink (conduction phenomenon), and also tak es into account the radiation and convection phenomena, The accuracy o f the model is evaluated with electrical and thermal characterizations , and with a validation circuit.