EMI EFFECTS AND TIMING DESIGN FOR INCREASED RELIABILITY IN DIGITAL-SYSTEMS

The failure modes of digital circuits subjected to low levels of elect romagnetic interference (EMI) are examined, While low-level EMI will n ot cause static failures (false switching), it may cause dynamic failu res by changing the propagation delays of critical signals. A paramete r called delay margin is introduced to define tile maximum allowable c hanges in propagation delay under which the circuit will continue to o perate reliably, Experimental results are reported in which circuit im munity to EMI is shown to increase significantly when the delay margin is maximized. It is also shown that delay-insensitive circuits have i nfinite delay margins and are therefore immune to low-level EMI. It wa s observed experimentally that an oscillating loop subjected to EMI ca n become phase locked to the frequency of the interference. The second part of the paper describes a synchronization scheme that takes advan tage of this phenomenon, The proposed scheme can he used to reduce err ors due to synchronizer metastability an communication links between s ynchronous and asynchronous systems, A reference signal derived from t he clock of the synchronous system is injected into a handshake loop, causing the data transfer rate to be locked to a subharmonic of the cl ock frequency. Both simulation and experimental results are given, sho wing that stable operation can be achieved over a wide range of parame ters.