ADVANCED METALLIZATION TECHNOLOGY FOR 256M DRAM

An advanced three-level interconnect technology for 0.25 mu m design r ule has been developed for a 256M DRAM process, that provides increase d circuit density, improved manufacturability and reduced cost. The pr ocess includes a polycide gate stack, self-aligned bitline contacts, a tungsten bitline, an Al-stitched wordline for the second level of met al and an Al global wiring level. Chemical-mechanical polishing (CMP) has been extensively used to improve planarity which increases the pro cess window for lithography and etch. This metallization concept has b een implemented on a 256M DRAM within the framework of a process archi tecture including a BuriEd STrap (BEST) trench memory cell and shallow trench isolation (STI). Five novel processes are discussed in detail. A self-aligned array contact using a highly selective etch process fo r SiO2/Si3N4, low epsilon IMD of fluorosilicate glass (FSG) deposited in a dual-frequency plasma CVD process (D-FSG) in comparison to HDP CV D and an alternative low-cost monolithic stud-wire concept using high temperature Al-PVD and planarization by a non-corrosive Al CMP. The '' Dual Damascene'' interconnects show improved electromigration resistan ce compared to RIE-patterned Al-sandwich structures on W studs.