INTER-METAL DIELECTRIC PLANARIZATION PROCESS FOR 0.35 MU-M MULTILEVELINTERCONNECTION DEVICES

A high inter-metal dielectric (IMD) planarization degree is requested in VLSI device manufacturing to avoid process degradation with increas ing number of interconnection layers. In this work an IMD planarizatio n process based on the use of spin on glass (SOG) for gap filling foll owed by SOG partial etch back (FEB) is presented. The main advantage o f this process is its capability to provide at the same time long rang e planarization with the ability to completely fill spaces between met al stripes 0.4 mu m wide with an aspect ratio (AR) greater than 2. The se results were obtained using a first oxide tapering process and maki ng use of a single thick SOG coating followed by PEB. The planarizatio n performances make the process suitable for the production of three a nd five metal level interconnection devices of 0.35 mu m technology, k eeping at the same time the process simple, cheap and highly repeatabl e.