DESIGN OF TESTABLE SEQUENTIAL-CIRCUITS BY REPOSITIONING FLIP-FLOPS

This paper presents a technique to enhance the testability of sequenti al circuits by repositioning flip-flops. A novel retiming for testabil ity technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundanci es, and yields retimed circuits that usually require fewer scan flip-f lops to break all cycles (except self-loops) as compared to the origin al circuit. Our technique is based on a new minimum cost flow formulat ion that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit graph to minimize the numbe r of flip-flops in the SCCs. A circuit graph has a vertex for every ga te, primary input and primary output, If gate a has a fanout to gate b , then the circuit graph has an are from vertex a to vertex b, Experim ental results on several large sequential circuits demonstrate the eff ectiveness of the proposed retiming for testability technique in reduc ing the number of partial scan flip-flops.