A NEW GAAS MMIC PROCESS TECHNOLOGY USING 0.5-MU-M GATE ASYMMETRIC LDDSTRUCTURE GAAS BP-MESFETS COMBINED WITH HIGH-DIELECTRIC-CONSTANT THIN-FILM CAPACITORS

A fabrication process of 0.5 mu m gate GaAs-MESFETs combined with high -dielectric-constant thin-film capacitors was investigated. A buried p layer (BP) is employed to suppress short-channel effects by using the carbon ion implantation technique. These BP-MESFETs have a self-align ed n(+) asymmetric lightly doped drain (LDD) structure to realize low source resistance and high drain breakdown voltage. The planarization technique was adopted to deposit an Au overlayer on top of the 0.5 mu m WSi gate to improve the high-frequency performance by reducing the g ate resistance. These BP-MESFETs have a high K value, over 230 mA V-2 mm(-1), and a maximum frequency of oscillation f(max) of 60 GHz with a n n(+) asymmetric structure. We also have developed high-dielectric co nstant SrTiO3 thin-film capacitors by using the low-temperature RF spu ttering method. These SrTiO3 films have high epsilon(r), over 100, and low leakage current density, under 1 x 10(-6) A cm(-2) at 1 MV cm(-1) . By using this SrTiO3 capacitor for the bypass capacitors of the MMIC , we can reduce the pin counts of the MMIC and will be able to realize a shrinkage of the total size of the RF unit of a cellular telephone. We have fabricated the front-end IC of a cellular telephone using thi s newly developed process technology, and can achieve low power consum ption.