SHARED-MEMORY ARCHITECTURE TO IMPLEMENT A HIGH-CONNECTIVITY PROCESSING NODE

Authors
ANCONA F ANGUITA D ROVETTA S ZUNINO R
Citation
F. Ancona et al., SHARED-MEMORY ARCHITECTURE TO IMPLEMENT A HIGH-CONNECTIVITY PROCESSING NODE, Electronics Letters, 31(22), 1995, pp. 1903-1904
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
31
Issue
22
Year of publication
1995
Pages
1903 - 1904
Database
ISI
SICI code
0013-5194(1995)31:22<1903:SATIAH>2.0.ZU;2-F
Abstract
The Letter describes the implementation of a high-connectivity process ing node by means of an embedded shared dual-port memory. The memory i s accessed directly by two transputers in order to realise a virtual p rocessor with a connectivity and a computing power that are twice thos e of a single transputer.