APPLICATION OF FILTER SHARPENING TO CASCADED INTEGRATOR-COMB DECIMATION FILTERS

A new architecture for the implementation of high-order decimation fil ters is described, It combines the cascaded integrator-comb (CIC) mult irate filter structure with filter sharpening techniques to improve th e filter's passband response, This allows the first-stage CIC decimati on filter to be followed by a fixed-coefficient second-stage filter, r ather than a programmable filter, thereby achieving a significant hard ware reduction over existing approaches, Furthermore, the use of fixed -coefficient filters in place of programmable-coefficient filters impr oves the overall throughput rate, The resulting architecture is well s uited for single-chip VLSI implementation with very high data-sample r ates, Applications include all-digital subband tuning for wide-band co mmunication links and signal analysis.