HIGH-PERFORMANCE VLSI ARCHITECTURE FOR THE VITERBI ALGORITHM

The Viterbi algorithm (VA) is characterized by a graph, called a trell is, which defines the transitions between states, To define an area ef ficient architecture for the VA is equivalent to obtaining an efficien t mapping of the trellis, In this paper, we present a methodology that permits the efficient hardware mapping of the VA onto a processor net work of arbitrary size, This formal model is employed for the partitio ning of the computations among an arbitrary number of processors in su ch a way that the data are recirculated, optimizing the use of the E's and the communications, Therefore, the algorithm is mapped onto a col umn of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints, Furthermore, th e management of the surviving path memory for its mapping and distribu tion among the processors was studied, As a result, we obtain a regula r and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data reci rculations between stages.