THE GMICRO 500 SUPERSCALAR MICROPROCESSOR WITH BRANCH BUFFERS

Featuring a RISC-like dual-pipeline structure for high-speed execution of basic instructions, the Gmicro/500 represents a significant advanc e for the TRON architecture. Upwardly object-compatible with earlier m embers of the Gmicro series, this microprocessor uses resident dedicat ed branch buffers to greatly enhance branch instruction execution spee d. Also, its microprograms simultaneously employ dual execution blocks to effectively execute high-level language instructions. Fabricated w ith a 0.6-mum CMOS technology on a 10.9 x 16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.