SCREENING ICS ON THE BARE CHIP LEVEL - TEMPORARY PACKAGING

Several different temporary packaging concepts of integrated circuits (IC's) for pretest at speed and burn-in are introduced. Temporary pack aging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to vali date the pretest process, and results are presented for the various ma terials used in the pretest process. The preferred method for temporar y packaging along with the selected materials used is presented. Tempo rary packaging of integrated circuits for pretest with reasonable yiel d is demonstrated as feasible.