A 20-GB S FLIP-FLOP CIRCUIT USING DIRECT-COUPLED FET LOGIC/

Citation
M. Shikata et al., A 20-GB S FLIP-FLOP CIRCUIT USING DIRECT-COUPLED FET LOGIC/, IEEE journal of solid-state circuits, 28(10), 1993, pp. 1046-1051
Citations number
8
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
28
Issue
10
Year of publication
1993
Pages
1046 - 1051
Database
ISI
SICI code
0018-9200(1993)28:10<1046:A2SFCU>2.0.ZU;2-W
Abstract
A new type of direct-coupled FET logic (DCFL) flip-flop called the mem ory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops as well as enhances the advantages o f DCFL such as low power consumption or high packing density. A D-flip -flop IC and a 1/8 divider IC were developed using the MCFF. These IC' s were fabricated using 0.2-pm-gate pseudomorphic inverted HEMT's. The D-flip-flop IC is confirmed to operate up to 20 Gb/s by an originally developed measurement system. The 1/8 divider is toggled up to a maxi mum frequency of 25 GHz. These results prove that the MCFF enables DCF L circuits applicable not only for LSI but for SSI or MSI operating up to 20 Gb/s.