IMPLEMENTING PRECISE INTERRUPTIONS IN PIPELINED RISC PROCESSORS

Pipelining is an important implementation technique that exploits para llelism among instructions. Imprecise interruption problems arise when a pipelined processor has multiple multicycle functional units becaus e instruction completion might be out of order. An early issued, long- running instruction might generate an interruption after the completio n of several short-running instructions issued later, resulting in an imprecise interruption. Here we investigate, from a VLSI implementatio n point of view, four solutions to the imprecise interruption problem in a pipelined reduced instruction-set computer processor having multi ple functional units.