A 700-MHZ 24-B PIPELINED ACCUMULATOR IN 1.2-MU-M CMOS FOR APPLICATIONAS A NUMERICALLY CONTROLLED OSCILLATOR

To accomplish timing recovery/synthesis in high-speed communication sy stems, a 24-b numerically controlled oscillator (NCO) IC using a circu it design technique called true single-phase clock (TSPC) pipelined CM OS has been fabricated in a standard 1.2-mum CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results i n an output frequency tuning range from dc up to 350 MHz with a 41.7-H z tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7 x 1.7-mm2 IC dissipates 850 mW with a single 5-V supply, which is sub stantially lower than similar ECL and GaAs devices.