THE USE OF STABILIZED CMOS DELAY-LINES FOR THE DIGITIZATION OF SHORT-TIME INTERVALS

Authors
RAHKONEN TE KOSTAMOVAARA JT
Citation
Te. Rahkonen et Jt. Kostamovaara, THE USE OF STABILIZED CMOS DELAY-LINES FOR THE DIGITIZATION OF SHORT-TIME INTERVALS, IEEE journal of solid-state circuits, 28(8), 1993, pp. 887-894
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
28
Issue
8
Year of publication
1993
Pages
887 - 894
Database
ISI
SICI code
0018-9200(1993)28:8<887:TUOSCD>2.0.ZU;2-X
Abstract
This paper discusses the basic advantages and limitations of using int egrated digital CMOS delay lines for the digitization of short time in tervals. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 1 0 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measur ement.