LARGE-SCALE INTEGRATION FOR HIGH-SPEED JOSEPHSON RANDOM-ACCESS MEMORY

A guiding principle is proposed for designing a large scale integrated high-speed Josephson RAM. This principle addresses the following impo rtant issues in high-speed operation; (i) the reduction of memory cell size, (ii) a decrease in the total inductance of one control line on the memory cell array and (iii) the use of impedance-matched lines as signal lines. In addition, reducing the power consumption is also a si gnificant issue because large scale integrated and high-speed circuits generally induce large power dissipation. To reduce the power dissipa tion, it is necessary to reduce the number of current injection gates or decrease operating currents. According to the guiding principle, we have designed 16-Kbit Josephson RAM's in the both cases that using de coders with ''AND'' gates and using decoders with ''NOR'' gates. The f ormer is aimed at high-speed operation, and the latter gives the first priority to decreasing the power consumption. In these two cases, the access times, 360psec and 480psec, and power consumption, 22mW and 14 mW, are estimated.