The advent of High-Tc materials has generated excitement for developin
g faster and more reliable superconducting computer systems. The new m
aterials allow for the use of relatively inexpensive cryo-coolers, all
owing portability and furthering interest in space-based on-board proc
essing. Presently-available YBCO junctions are, however, naturally dam
ped SNS devices which do not have the hysteresis that most traditional
superconducting circuits rely upon. A simple alternative to these arc
hitecture is the SAIL architecture we have developed at TRW 1). These
are composed of a Series Array of dc SQUIDs (Interferometer Logic), an
d use non-hysteretic devices. It is much like CMOS semiconductor desig
ns, including the voltage bias, in contrast to current bias more typic
al of superconducting circuits. Further, it relies on only a few SQUID
s to implement all of the binary logic functions, including a very nat
ural invertor, without recourse to dual-rail outputs. Since the logica
l function of a gate is determined by the final wiring layer, gate arr
ay applications are a natural use of this architecture. In 1991 we pub
lished a demonstration of low speed operation using then available YBa
2Cu3O7 dc SQUIDs 2). These tests showed that the devices will work usi
ng supplied voltage rails and do not latch at intermediate voltages as
early models had predicted. Our current efforts are geared toward pla
cing much improved devices 3),4) in this architecture and testing at h
igh (2 GHz and higher) speed at higher temperatures (above 65 K). Our
modelling indicates that generally speed will be limited by the induct
ive input coils, a problem not faced by RSFQ 5) logic for example. The
larger SAIL operating margins, it's simplicity of design, and more ge
nerous production latitude will allow early use in many important appl
ication. SAIL modelling and experimental results will be compared to o
ther designs, and RSFQ -in particular, with respect to speed, performa
nce, and margins.