A FAST BINARY ADDER WITH CONDITIONAL CARRY GENERATION

This brief contribution presents a fast binary adder in static CMOS re alization. While the carry derivation is similar to that in a conditio nal-sum adder, the proposed adder is also similar to that of a spannin g tree carry lookahead adder in the sense that only selected carry bit s are generated and the sum bits are produced by carry-select adders. In a 1.2 mu m static CMOS realization, the proposed adder adds two 32- bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.