SYNCHRONIZATION OF PIPELINES

In this paper we apply a recently formulated general timing model of s ynchronous operation to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, cor rectly captures the behavior of level-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads t o a comprehensive set of timing constraints. Pipeline circuits are imp ortant because of their frequent use in computer systems. We define th eir concurrency as a function of the clock schedule and degree of wave pipelining. We then identify a special class of clock schedules, coin cident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. We show that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and deriv e a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking. We compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization.