DELAY-FAULT TEST-GENERATION AND SYNTHESIS FOR TESTABILITY UNDER A STANDARD SCAN DESIGN METHODOLOGY

We address the problems of test generation and synthesis aimed at prod ucing VLSI sequential circuits that are delay-fault testable under a s tandard scan design methodology. We begin with theoretical results reg arding the standard-scan delay testability of finite state machines (F SM's) described at the state transition graph (STG) level. We show tha t a one-hot coded and optimized FSM whose STG satisfies a certain prop erty is guaranteed to be fully gate-delay-fault testable under standar d scan. We extend this result to arbitrary-length encodings and develo p a heuristic state assignment algorithm that results in highly gate-d elay-fault testable sequential FSMs, which are also area-efficient, as evinced by results obtained on benchmark FSM circuits. We switch focu s to the problem of delay test generation for large sequential circuit s and modify a PODEM-based combinational test pattern generator for ou r purpose. The modifications involve a two time-frame expansion of the combinational logic of the circuit, and the use of backtracking heuri stics tailored for our problem. We also employ a version of the scan s hifting technique in our test pattern generator. We give an algorithm to determine an efficient ordering of the flip-flops in the scan-chain using the information derived from running a delay test generator on the circuit. Given an ordering of the flip-flops, we give an optimizat ion algorithm that attempts to minimize the number of flip-flops to be made enhanced-scan so as to obtain a required level of delay-fault co verage. We show how the test vector sets derived using our test genera tor can be compacted by solving a clique covering problem. We present test generation, flip-flop ordering, flip-flop selection and test set compaction results on large benchmark circuits.