AN ASIP INSTRUCTION SET OPTIMIZATION ALGORITHM WITH FUNCTIONAL MODULESHARING CONSTRAINT

One of the most interesting and most analyzed aspects of the CPU desig n is the instruction set design. How many and which operations to be p rovided by hardware is one of the most fundamental issues relating to the instruction set design. This paper describes a novel method that f ormulates the instruction set design of ASIP (an Application Specific Integrated Processor) using a combinatorial approach. Starting with th e whole set of all possible candidate instructions that represent a gi ven application domain, this approach selects a subset that maximizes the performance under the constraints of chip area, power consumption, and functional module sharing relation among operations. This leads t o the efficient implementation of the selected instructions. A branch- and-bound algorithm is used to solve this combinatorial optimization p roblem. This approach selects the most important instructions for a gi ven application as well as optimizing the hardware resources that impl ement the selected instructions. This approach also enables designers to predict the performance of their design before implementing them, w hich is a quite important feature for producing a quality design in re asonable time.