PRECISENESS OF DISCRETE-TIME VERIFICATION

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discret e time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all po ssible delay cases under the discrete time. Our main theorem is as fol lows: refine the unit time by a factor of 1/2, and if the analysis res ult with a unit time u and that with a unit time u/2 are the same, the n u is the expected unit time.