TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING PARTITIONED IMAGE COMPUTATION

This letter presents an algorithm named SPM which generates test patte rns for single stuck-at faults in synchronous sequential circuits base d on a product machine traversal method. The new idea presented in thi s letter is partitioned image computation combined with a mixed breadt h-first/depth-first search. Image computation is carried out in partit ioned manner by substituting constant logical values to some input var iables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 bench-mark circuits with not more t han 32 flip-flops.