A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

Authors
BARTOLONI A BASTIANELLO G BATTISTA C CABASINO S MARZANO F PAOLUCCI PS PECH J RAPUANO F PANIZZI E SARNO R TODESCO GM TORELLI M TROSS W VICINI P CABIBBO N FUCCI A TRIPICCIONE R
Citation
A. Bartoloni et al., A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE, International journal of modern physics C, 4(5), 1993, pp. 969-976
Citations number
11
Categorie Soggetti
Mathematical Method, Physical Science","Physycs, Mathematical","Computer Applications & Cybernetics
Journal title
International journal of modern physics C → ACNP
ISSN journal
01291831
Volume
4
Issue
5
Year of publication
1993
Pages
969 - 976
Database
ISI
SICI code
0129-1831(1993)4:5<969:AHIOTA>2.0.ZU;2-J
Abstract
APE100 processors are based on a simple Single Instruction Multiple Da ta architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.