A HIGH-LEVEL APPROACH TO TEST-GENERATION

Citation
P. Narain et al., A HIGH-LEVEL APPROACH TO TEST-GENERATION, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 40(7), 1993, pp. 483-492
Citations number
29
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
10577122
Volume
40
Issue
7
Year of publication
1993
Pages
483 - 492
Database
ISI
SICI code
1057-7122(1993)40:7<483:AHATT>2.0.ZU;2-P
Abstract
High-level test generation has recently been the focus of a lot of res earch. However, a study into the nature of high-level test generation algorithms has not been conducted. In this paper, we present a high-le vel test generation algorithm based upon the branch and bound search p rocedure. We describe the algorithm in detail, bringing out the variou s trade-offs that are involved. Chronological backtracking schemes are simple, but become ineffective with the increase in the size of the c ircuits. We introduce a complete dependency directed backtracking sche me that has significant advantage over chronological backtracking. We present different usage schemes for our algorithm to show its versatil ity. We also present results showing significant performance improveme nt over gate level test generation using this scheme. The ability to g enerate tests for incomplete designes is a major strength of this sche me.