P. Narain et al., A HIGH-LEVEL APPROACH TO TEST-GENERATION, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 40(7), 1993, pp. 483-492
High-level test generation has recently been the focus of a lot of res
earch. However, a study into the nature of high-level test generation
algorithms has not been conducted. In this paper, we present a high-le
vel test generation algorithm based upon the branch and bound search p
rocedure. We describe the algorithm in detail, bringing out the variou
s trade-offs that are involved. Chronological backtracking schemes are
simple, but become ineffective with the increase in the size of the c
ircuits. We introduce a complete dependency directed backtracking sche
me that has significant advantage over chronological backtracking. We
present different usage schemes for our algorithm to show its versatil
ity. We also present results showing significant performance improveme
nt over gate level test generation using this scheme. The ability to g
enerate tests for incomplete designes is a major strength of this sche
me.