FABRICATION OF TUNGSTEN LOCAL INTERCONNECT FOR VLSI BIPOLAR TECHNOLOGY

We have developed a process for fabricating thin W films for local int erconnect applications in circuits using Si bipolar transistors. Tungs ten films deposited by both sputtering and chemical vapor deposition ( CVD) methods were patterned over topography with a highly anisotropic and selective single-wafer reactive ion etch (RIE) process in Cl2 and O2. Maze structures were tested electrically to characterize the opens and shorts yield. In addition, the profiles of etched lines were char acterized by cross-sectional scanning electron microscopy. High yields (>80%) were obtained for a wide range of RIE conditions on mazes of v ariable pitch (minimum 1.8 mum) with lengths >0.5 m. Yields were furth er increased using a simple ''semi-planarization'' of the underlying s ubstrate prior to metal deposition. With a composite sputtered and CVD W bilayer (total thickness 350 nm), a local interconnect sheet resist ance of <0.5 OMEGA/square was obtained with minimal topography added t o the overall device structure. As a technological demonstration, devi ce characteristics of a submicron bipolar circuit fabricated with sput tered tungsten local interconnect were measured. Near ideal Gummel cha racteristics were obtained, and emitter-coupled-logic ring oscillator gate delays of 38 ps were measured at a switch current density of 0.6 mA/mum2.