This paper deals with testing of digital circuits, spectral techniques
, and neural networks: It shows how an optimization problem that appea
rs in the design of concurrent testable circuits can be expressed by u
sing digital spectral techniques in such a way that makes it possible
to compute an acceptable solution by using neural networks. To build a
concurrent testable circuit, it is necessary to use some specific che
cking circuitry for analyzing the outputs of that circuit while it is
in operation. The goal is to find the checking circuitry that, with le
ss hardware complexity than a given bound, allows us to detect as many
errors as possible at the outputs of the circuit under test. This pap
er provides a measure, the aliasing probability, to evaluate the perfo
rmances of the checking circuitry. It also shows how, by using spectra
l techniques based on the Reed-Muller transform, the aliasing probabil
ity can be expressed as a function of the Reed-Muller coefficients. In
this way, to obtain the checking circuitry means to select a set of R
eed-Muller spectral coefficients, with less elements than a given boun
d, that minimizes the aliasing probability: It is an NP-complete probl
em as in the majority of combinatorial optimization problems. It has b
een suggested [1] that neural networks, in particular the Hopfield neu
ral network, may be used to solve combinatorial optimization problems,
as it always moves toward decreasing an energy function that is quadr
atic in terms of the processor states. To apply the neural networks to
design the checking circuitry for concurrent testing, the aliasing pr
obability has been used as an energy function, and the Hopfield neural
network has been modified to have an associated energy function with
any type of polynomial dependence on the processor states. This paper
analyzes the so-called generalized Hopfield neural network, considers
its application to solve optimization problems with an objective funct
ion taking any nonlinear form, and, as an example, uses the generalize
d Hopfield network in the design of the extra modules of a concurrent
testable circuit.