PLS - A SCHEDULER FOR PIPELINE SYNTHESIS

Pipelining is an effective method to optimize the execution of a loop, especially for digital signal processing (DSP) applications where dat a enter a circuit regularly. Although throughput and delay are two imp ortant optimization criteria, previous work emphasizes mainly on the t hroughput. We show that the delay time of executing an iteration of a loop has a strong relationship with the cost of the registers and the controller. By minimizing the delay, we could have more silicon area t o allocate additional resources which in turn will increase throughput . We iteratively use a forward scheduling and a backward scheduling to achieve this purpose. The algorithm can be used to pipeline a loop wi th or without loop carried dependencies. Real examples are used to ill ustrate the proposed method. Experiments on benchmark examples show th at the new approach pains a considerable improvement over those by pre vious approaches.