FAULT SIMULATION OF PARAMETRIC BRIDGING FAULTS IN CMOS ICS

The fault simulation of resistive bridging faults inside complex CMOS macro-gates requires proper evaluation of resistances, in order to cor rectly determine realistic fault coverages. To this purpose, the prese nt work illustrates a novel approach applicable to a large category of faults (bridgings, transistor stuck-ons and node stuck-ats) giving ri se to resistive paths between power-supply and ground, hence being all indicated by the general term of ''bridging faults.'' Such a method, avoiding single-fault injection procedure, consists of a fault analysi s performed inside macro-pates aimed at determining the threshold resi stance discriminating whether or not a given fault is detectable as a logic error; this analysis is performed inside CMOS macro-gates whose output is observable, as determined by means of any method and/or simu lator. Finally, to fully characterize the quality of a test sequence w ith regard to resistive bridging faults, a new definition of fault cov erage is presented, because the common concept of fault detection is n ot applicable to parametric faults.