21-PS 0.1-MU-M CMOS DEVICES OPERATING AT ROOM-TEMPERATURE

Citation
T. Izawa et al., 21-PS 0.1-MU-M CMOS DEVICES OPERATING AT ROOM-TEMPERATURE, IEEE electron device letters, 14(11), 1993, pp. 533-535
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
07413106
Volume
14
Issue
11
Year of publication
1993
Pages
533 - 535
Database
ISI
SICI code
0741-3106(1993)14:11<533:20CDOA>2.0.ZU;2-N
Abstract
High-speed complementary metal-oxide semiconductor (CMOS)-inverter rin g oscillators with the shortest gate length of 0.17 mum were fabricate d by a conventional large-scale integrated (LSI) technology. The propa gation delays were 21 ps/stage (2.0 V) at room temperature and 17 ps/s tage (2.0 V) at 80 K. These results are the fastest records as reporte d for bulk CMOS devices as of today. The results were obtained by redu cing effective drain junction capacitances with ''double-finger gates, '' and devices will probably be faster if the areas are completely pro portionally reduced to the feature size. Though it is important for CM OS devices to increase drain currents, a silicidation technique for so urce and drain was not necessary for the tested devices to reduce seri es resistance.