CLOCK SUPPRESSION TECHNIQUES FOR SYNCHRONOUS CIRCUITS

In 1990, the authors presented an outline for a clock suppression base d technique that took advantage of the higher abstraction level provid ed by synchronous design techniques to improve logic simulation perfor mance [1]. This paper will elaborate on those techniques and present e xtensions that can offer an average performance increase of over 5x an d a peak performance increase of over 10x that of a conventional logic simulator. We shall show the viability of our approach by presenting results from switch-level simulations of large industrial examples. Fi nally, we shall demonstrate that because clock suppression based techn iques are CPU-bound, they can take advantage of the recent explosive g rowth of CPU performance.