FAULT SIMULATION OF LINEAR ANALOG CIRCUITS

Research in the areas of analog circuit fault simulation and test gene ration has not achieved the same degree of success as its digital coun terpart owing to the difficulty in modeling the more complex analog be havior. This article presents a novel approach to this problem by mapp ing the good and faulty circuits to the discrete Z-domain. An efficien t fault simulation is then performed on this discretized circuit for t he given input test wave form. This simulator provides an order of mag nitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the gro und for analog automatic test generation.