2-STEP ANNEALS TO AVOID BRIDGING DURING CO SILICIDATION

A two-step rapid thermal process has successfully been applied for the simultaneous Co silicidation of source/drain and gate areas in MOS te st structures while avoiding lateral creep or bridging. The method is based on the formation of CoSi on the active areas and poly-Si gate li nes during the first RTP step, while keeping the thermal budget suffic iently low in order not to form this silicide phase on the spacers. Fo llowing a selective etch, a second RTP step leads to the formation of CoSi2. After sputtering of 20 nm Co on either undoped or doped wafers, RTP was done at 487 degrees C for 30 s to form CoSi. A subsequent sel ective etch and a second RTP step heating the wafer up to 850 degrees C, resulted in a sheet resistance of 3-6 Ohm/rectangle on both the act ive areas and poly-Si gate lines. A ''non-bridging'' yield, which is i n all cases close to 100%, has been found, irrespective of the conside red processing parameters.