CMOS 4-QUADRANT MULTIPLIER USING BIAS OFFSET CROSSCOUPLED PAIRS

Authors
LIU SI HWANG YS
Citation
Si. Liu et Ys. Hwang, CMOS 4-QUADRANT MULTIPLIER USING BIAS OFFSET CROSSCOUPLED PAIRS, Electronics Letters, 29(20), 1993, pp. 1737-1738
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
29
Issue
20
Year of publication
1993
Pages
1737 - 1738
Database
ISI
SICI code
0013-5194(1993)29:20<1737:C4MUBO>2.0.ZU;2-V
Abstract
A CMOS four-quadrant multiplier using bias offset crosscoupled pairs i s presented. Simulation results show that for a power supply of +/- 5V , the linearity error is less than 1% over a +/- 2.5V input range. The effect of mobility reduction is also analysed. The results will be us eful in analogue signal processing applications.