REALIZATION OF HIGH-SPEED SYSTOLIC IIR DECIMATORS AND INTERPOLATORS

Two novel systolic allpass digital filtering arrays for realising high -speed systolic IIR decimators and interpolators are described. The sa mpling period at the input of such a decimator by N and at the output of such an interpolator by N can be reduced to (T(m)+2T(a))/(N-1) and (T(m)+3T(a))/N, respectively, by the two arrays. (T(m) and T(a), respe ctively, represent the times for two-input real multiplication and two -input real addition.) Other advantages include reduced latencies, and reduced numbers of multipliers and adders.