THE NO SLOT WASTING BANDWIDTH BALANCING MECHANISM FOR DUAL BUS ARCHITECTURES

Citation
D. Karvelas et M. Papamichail, THE NO SLOT WASTING BANDWIDTH BALANCING MECHANISM FOR DUAL BUS ARCHITECTURES, IEEE journal on selected areas in communications, 11(8), 1993, pp. 1214-1228
Citations number
13
Categorie Soggetti
Telecommunications,"Engineering, Eletrical & Electronic
ISSN journal
07338716
Volume
11
Issue
8
Year of publication
1993
Pages
1214 - 1228
Database
ISI
SICI code
0733-8716(1993)11:8<1214:TNSWBB>2.0.ZU;2-I
Abstract
A Bandwidth Balancing (BWB) mechanism has been recently added to the d istributed queueing algorithm of DQDB. BWB can provide the requested t hroughputs by lightly loaded stations and evenly distribute the remain ing channel bandwidth among overloaded stations. However, its operatio n requires the wastage of channel slots. In this paper, we introduce a new bandwidth balancing mechanism for DQDB. The operation of the new mechanism requires one additional bit in the Access Control Field (ACF ) of the slot but has the advantage of exhibiting a similar behavior w ith the current BWB mechanism of DQDB without wasting any channel slot s. For this reason, it can converge faster to the steady state where f air bandwidth allocation is achieved. We investigate the throughput an d delay performance of the proposed mechanism under one traffic class and examine its capacity to support multiple priority classes of traff ic. We also compare its performance with the corresponding performance of the BWB mechanism of DQDB.