THERMAL LIMITS OF FLIP-CHIP PACKAGE - EXPERIMENTALLY VALIDATED, CFD SUPPORTED CASE-STUDIES

This study projects the thermal performance limits of a hip chip packa ge, A plastic, pin grid array (PGA) package with direct chip attach (D CA) interconnect was chosen for the demonstration purpose. Same method ology as developed here can be applied to other hip chip packages. The design rules chosen are the allowable power dissipation for constrain ts of junction temperature (less than or equal to 105 degrees C) and b oard temperature (less than or equal to 90 degrees C) under either fre e air or forced air (1.27 m/s) condition. An experimentally validated computational fluid dynamics (CFD) model was used to predict the therm al performance limits of the flip chip package, Simulations were run b y increasing the power to the package under consideration until either the junction temperature or the board temperature reached its limit, Based on these constraints, the allowable power dissipation in the pac kage was determined to be between 1.7 and 6.7 W in free air and betwee n 2.1 and 13.7 W in 1.27 m/s of air. The validated CBD models offer en ormous potential to quickly asses thermal limits of many future flip c hip packages and their variations.