Material research on capacitor dielectrics for DRAM applications is re
viewed. The state of the art technologies to prepare Si3N4, Ta2O5, and
SrTiO3 thin films for capacitors are described. The down-scaling limi
ts for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equiv
alent thickness, respectively. Combined with a rugged polysilicon elec
trode surface, Si3N4 and Ta2O5 based-capacitors are available for 256
Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalen
t thickness for high permittivity materials is around 1 nm with the le
akage current density of 10(-7) A/cm2. Among the great variety of ferr
oelectrics, two families of materials, i.e., Pb (Zr, Ti) O3 and (Ba, S
r) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs
and beyond. If the chemical vapor deposition technology can be establ
ished for these materials, capacitor dielectrics should not be a limit
ing issue for Gbit DRAMs.